1. Field of the Invention
This invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device including a memory transistor of the SAMOS type having a floating gate and a control gate and a peripheral transistor of the MOS type and a method for manufacturing such a semiconductor device.
2. Description of the Prior Art
Heretofore, wide use has been made of a semiconductor memory including a SAMOS type memory cell in which a control gate is provided above a floating gate, with an insulating layer sandwiched therebetween. In comparison with FAMOS type memory cells, in such a SAMOS type memory, there is a characteristic feature of high reliability in performance such as excellence in controlling write-in voltage and a capability to monitor the write-in condition. The typical structure of a semiconductor memory including such a prior art SAMOS type memory cell is illustrated in FIG. 1.
The prior art semiconductor device shown in FIG. 1 includes a substrate 1 comprised of a semiconductor material, typically silicon, in the surface of which are formed field oxides 2a, 2b and 2c thereby defining device regions 3a and 3b between the two adjacent field oxides. In the device region 3a there is formed a SAMOS transistor as a memory cell. That is, in the surface of the device region 3a, diffused regions 4a and 4b are formed by having an impurity opposite in conductivity type to the substrate 1 doped into the substrate 1. Provided on the surface of the substrate as extending between the pair of diffused regions 4a and 4b is an insulating layer 5a, on the surface of which is formed a floating gate 6a which is typically formed by doped polycrystalline silicon, or simply polysilicon. On the floating gate 6a is formed an interlayer oxide film 7, on which is formed a control gate 8 typically from doped polysilicon.
On the other hand, in the device region 3b which is laterally separated from the device region 3a by the field oxide layer 2b, there is formed a common MOS transistor. Stated in greater detail, in the surface of the substrate 1 is formed a pair of diffused regions 4c and 4d spaced apart from each other over a predetermined distance, and, similarly with the case of the diffused regions 4a and 4b, these diffused regions 4c and 4d are also formed by doping an impurity opposite in the type of conductivity to the substrate 1. An insulating layer 5b is formed on the surface of the substrate, extending between the pair of diffused regions 4c and 4d, and a gate 6b, typically of doped polysilicon, is formed on the insulating layer 5a. Furthermore, on the field oxide 2b there is formed an interconnection layer 9 which is used for establishing interconnections between devices formed in device or active regions.
Now, a description will be given of a prior art method for manufacturing the semiconductor device having the structure shown in FIG. 1. In the first place, the surface of the substrate 1 is selectively oxidized in a well-known manner to form the field oxide layers 2a, 2b and 2c thereby defining the device or active regions 3a and 3b. Although not shown in FIG. 1, gate oxidation is carried out after the selective oxidation to form a thin insulating layer formed by an oxide of the substrate 1 across the surface of each of the device regions 3a and 3b. Then, a first layer of polysilicon is formed across the entire surface, which is then patterned. In this instance, the floating gate 6a is formed from the first layer of polysilicon, the rest of which is etched away. Then, thermal oxidation is carried out to have the floating gate 6a of polysilicon paritially oxidized thereby forming the interlayer oxide layer 7. At this time, the gate oxide film for each of the peripheral transistors other than the memory transistors is also formed at the same time. Then, a second layer of polysilicon is formed across the entire surface, which layer is then selectively etched to form the control gate 8 as well as the gate electrode 6b in the device region 3b and the interconnection layer 9 on the field oxide layer 2b. Then, after patterning the interlayer insulating film 7 by etching, the first layer 6a of polysilicon to be formed into a floating gate is etched in self-alignment with the second layer 8 of polysilicon to be formed into a control gate.
In the prior art manufacturing method as described above, at the step of etching the interlayer insulating film, the substrate 1 is exposed at the diffused regions 4c and 4d in the device region 3b, so that these exposed portions of susbtrate 1 may become damaged at the following etching step by self-alignment. These damaged portions are shown in FIG. 1 as indicated by A. Such damage is disadvantageous because it can be a cause of metal shorting between interconnection lines. With reference to FIGS. 2a-2c and 3, a description will be given of such metal shorting between interconnection lines is produced due to such damage to the substrate 1. As shown in FIG. 2a, when the substrate 1 receives damaged caused by etching, the boundary between the field oxide 2b and the diffused region 4c is most liable to receive such damages and thus a groove 10 is formed as shown. Then, when a PSG layer 11 is formed across the entire surface, a valley 12 is formed at the similar location because of the presence of the groove 10 between the field oxide 2b and the diffused region 4c. Under the condition, if a layer of photoresist is formed and photoetching is carried out to form through-holes for electrical contact at desired locations, since the contact between the photoresist and the PSG layer 11 is poor at the valley 12, the etchant will penetrate into the interstices between the photoresist and the PSG layer 11 thereby causing undesired portions of the PSG layer 11 to be etched. In this manner, as shown in FIG. 2b, a groove 13 is formed in the PSG layer 11 along the side of the field oxide 2b. When metal interconnection is formed on the PSG layer 11 in the next step, metal remains in the groove 13, so that there is formed an unwanted metal pattern 16 along the boundary between the field oxide 2 and the diffused region 4.
As is clear from FIG. 3, such an unwanted metal pattern 16 would cause a metal interconnection 14, which is electrically connected to the diffused region 4 through a contact 14a, to be shorted to another metal interconnection 15 undesirably. In particular, one semiconductor device, has a centrally located memory region in which a number of memory transistors are arranged in the form of a two dimensional array, and a peripheral region surrounding the memory region in which a number of MOS transistors are provided and interconncted to define desired logic circuits such as decoders. In that example, the presence of such an unwanted metal line 16 can be a cause of electrical shorting between interconnection lines which can lower the yield in manufacture of semiconductor devices. Moreover, in the above-described prior art manufacturing method, the interlayer oxide film and the gate oxide film for each peripheral transistor are formed at the same time, so that if these oxide films are to be formed by thermal oxidation, during formation of the floating gate of memory transistor, impurities will flow out from the first layer 6a of polysilicon thereby causing the channel region of the peripheral transistor 3b to be autodoped. As a result, the threshold of the peripheral transistor tends to be more scattered, which also contributes to lowering of the yield.